As semiconductor devices continue to scale to smaller dimensions, the ability to pattern features becomes increasingly difficult. These difficulties include in one aspect the ability to obtain features at a target size for a given technology generation. Another difficult is the ability to obtain the correct shape of a patterned feature, as well as packing density, and the ability to obtain correct overlay to structures patterned in previous processing operations.
In another example, overlay error represents a challenge to extend lithography to advanced nodes. While multi-patterning has been used to address line width and line pitch reduction of features, overlay becomes an increasing challenge. One reason is as the feature line/space is reduced, the overlay requirement becomes smaller. A second reason is as multiple cut masks are coming into use, multiple overlay issues between cut masks and the other features on a substrate arise.
With respect to these and other considerations the present improvements may be useful.